The continual advancement in manufacturing technologies and the resultant process variations have caused performance variability (delay/timing, power) to become increasingly significant. Statistical models have become mandatory to model the performance variability. Due to the high complexity of the current VLSI and ULSI designs, existing models, algorithm or tools are not able to guarantee the accuracy and efficiency of the performance prediction at the same time.
The design and production of current generation integrated circuits that can include up to several million transistors is a very complex operation. Many sources of variation, such as device dimensions and environmental factors (power, temperature), can significantly impact the yield during the manufacturing stage. Accurately predicting what change may occur during the manufacture of a device due to one or more possible variations is of great value in optimizing a design to account for such variations. Current methods of predicting changes that may occur due to variations of design and/or manufacture typically involve the use of statistical distribution of design uncertainty and sampling models, such as Monte Carlo analysis, Latin Hypercube, and similar techniques. These methods, however, are generally disadvantageous in that they require significant processing overhead, time, and are not scalable.